With micronization of a semiconductor technology, a storage device mounted on an information processing apparatus, which is, e.g., a storage element included in a cache, is also micronized, with the result that an error becomes easy to occur due to inversion etc of storage information. Further, as for a circuit within the storage device, a margin of an adjustment value of internal operation timing is reduced for aiming at improving an operation frequency. When the margin is reduced, an operation condition of an operation-enabled voltage or temperature etc is restricted, so that there decreases resistance against, e.g., voltage fluctuations as exemplified by the fluctuations in signal voltage and source voltage or temperature fluctuations. Under such circumstances, the errors of different types and of different properties from those conventional types and properties come to occur.
Measures against the error caused in the storage device have hitherto involved conducting error correction based on, e.g., Error Correcting Code (ECC) and error detection based on a parity check, and so on.
On the other hand, such a technology is proposed as to avoid the error occurring in a cache Random Access Memory (RAM) etc by employing a cache line alternation register. If the error occurs in the cache RAM, the cache line containing an error portion is invalidated, and data is registered again in the cache RAM. Then, when having an access to the error portion of the cache RAM, data in the cache line alternation register is used in place of the data in the error portion, thus providing the data with no error.    [Patent Document 1] Japanese Patent Publication No. 4595029    [Patent Document 2] Japanese Patent Application Laid-Open Publication No. 1984-207099